1. Field of the Invention
The present invention relates to an automatic placement and routing apparatus used for designing a semiconductor integrated circuit including a plurality of power supply systems with different potentials.
2. Description of Related Art
A conventional automatic placement and routing apparatus and an automatic placement and routing method control the timing of a semiconductor integrated circuit by placement improvement that alters the cell placement, by routing improvement that alters the wiring length, width and spacing, and by logic improvement that alters the logic circuit.
FIG. 17 is a block diagram showing a configuration of a conventional automatic placement and routing apparatus. In FIG. 17, the reference numeral 101 designates an automatic placement and routing apparatus; 102 designates a cell library for storing cells; 103 designates a netlist describing logic connection information about the semiconductor integrated circuit; 104 designates timing constraint information about the semiconductor integrated circuit; 105 designates a layout design section for making a layout design of the semiconductor integrated circuit in accordance with the netlist 103 and timing constraint information 104 using the cells stored in the cell library 102; 106 designates an input section for a user of the automatic placement and routing apparatus 101 to input information needed for the layout design by the layout design section 105; and 107 designates a display section for displaying a layout design state in a specified layout design stage by the layout design section 105.
In the layout design section 105, the reference numeral 108 designates a link section for linking the netlist 103 with the cells stored in the cell library 102; 109 designates a placement and routing section for carrying out the placement, global routing and detail routing of the cells stored in the cell library 102 according to the netlist 103 and timing constraint information 104; 110 designates a timing verification section for carrying out the timing verification of specified paths according to the layout information after the placement and routing by the placement and routing section 109; and 111 designates a timing improvement section including a placement alteration section 112, a routing alteration section 113 and a logic alteration section 114. The placement alteration section 112 alters, when the timing verification detects a cell having a timing problem, the placement of the cell and its neighboring cells. The routing alteration section 113 alters the neighboring routing of the cell, and the logic alteration section 114 alters the neighboring logic circuit of the cell.
The placement and routing section 109 carries out, when the timing verification detects a cell having a timing problem, the replacement and rerouting of the altered portion in accordance with the alteration of the cell placement specified by the placement alteration section 112, the alteration of the routing specified by the routing alteration section 113 and the alteration of the logic circuit specified by the logic alteration section 114, thereby optimizing the layout. When the timing verification detects no cells having a timing problem, the placement and routing section 109 outputs layout information 115 and a netlist 116.
Next, the operation of the conventional automatic placement and routing apparatus will be described.
FIG. 18 is a flowchart illustrating the operation of the conventional automatic placement and routing method.
First, the link section 108 reads the netlist 103 that contains the logic connection information about the semiconductor integrated circuit, and links the netlist 103 to the cells stored in the cell library 102 (step ST201).
Subsequently, reading the netlist 103 linked to the cells stored in the cell library 102 and the timing constraint information 104 about the semiconductor integrated circuit, the placement and routing section 109 carries out the placement, global routing and detail routing of the cells stored in the cell library 102 in accordance with the netlist 103 and the timing constraint information 104 which are read out (step ST202).
Subsequently, the timing verification section 110 reads the layout information after the placement and routing by the placement and routing section 109, and carries out the timing verification of the specified paths in accordance with the layout information (step ST203).
Subsequently, when the timing verification detects a cell having a timing problem at step ST204, the placement alteration section 112 decides to alter the placement of the cell and its neighboring cells. In addition, the routing alteration section 113 decides to alter the routing of the cell and its neighboring cells, and the logic alteration section 114 decides to alter the logic circuit of the cell and its neighboring cells (step ST205).
Subsequently, the placement and routing section 109 reads information about the alterations of the cell placement determined by the placement alteration section 112, of the routing determined by the routing alteration section 113 and of the logic circuit determined by the logic alteration section 114 to carry out the replacement and rerouting of the altered portion in accordance with these altered items of information, thereby optimizing the layout (step ST206).
Subsequently, the timing verification section 110 reads the optimized layout information, and carries out the timing verification of the specified paths in accordance with the layout information (step ST203).
When the timing verification detects no cells having a timing problem at step ST204, the placement and routing section 109 outputs the layout information 115 and netlist 116 (step ST207).
The procedure from step ST203 to step ST206 is carried out until the timing verification detects no cell having the timing problem at step ST204, that is, until the timing constraint is satisfied.
FIG. 19 is a layout diagram of the semiconductor integrated circuit completed by the conventional automatic placement and routing apparatus and automatic placement and routing method. FIG. 20 is a circuit diagram of the circuit formed in accordance with the layout of FIG. 19. In these figures, reference numerals 121–124 designate first to fourth cells. The first to fourth cells 121–124 each denote an inverter comprising intra-cell mains at its top and bottom sides. The reference numeral 125 designates a first power supply main including an upper intra-cell main of the first cell 121 and an upper intra-cell main of the second cell 122 as its part; and 126 designates a second power supply main including a lower intra-cell main of the third cell 123 and a lower intra-cell main of the fourth cell 124 as its part. The first power supply main 125 and the second power supply main 126 have the same potential. The reference numeral 127 designates a ground main including as its part the lower intra-cell main of the first cell 121, the lower intra-cell main of the second cell 122, the upper intra-cell main of the third cell 123 and the upper intra-cell main of the fourth cell 124.
The first and second cells 121 and 122 are disposed in such a manner that the upper intra-cell main of the first cell 121 is connected with that of the second cell 122, and the lower intra-cell main of the first cell 121 is connected with that of the second cell 122. In addition, the third and fourth cells 123 and 124 are disposed in such a manner that the upper intra-cell main of the third cell 123 is connected with that of the fourth cell 124, and the lower intra-cell main of the third cell 123 is connected with that of the fourth cell 124. Furthermore, the first and second cells 121 and 122, and the third and fourth cells 123 and 124 are placed in such a manner that the lower intra-cell mains of the first and second cells 121 and 122 overlap the upper intra-cell mains of the third and fourth cells 123 and 124.
In each of the first to fourth cells 121–124, the reference numeral 128 designates a gate electrode of a PMOS transistor; 129 designates a gate electrode of an NMOS transistor; 130 designates an active region of the PMOS transistor; 131 designates an active region of the NMOS transistor; 132 designates a first metal interconnection connected to the source region of the PMOS transistor; 133 designates a second metal interconnection connected to the source region of the NMOS transistor; 134 designates a third metal interconnection for connecting the gate electrode 128 of the PMOS transistor with the gate electrode 129 of the NMOS transistor, which gate electrodes function as an input terminal; and 135 designates a fourth metal interconnection for connecting the drain region of the PMOS transistor with that of the NMOS transistor, which drain regions function as an output terminal.
The reference numeral 136 designates a first signal line connected to the third metal interconnection 134 serving as the input terminal of the first cell 121; 137 designates a second signal line connected to the fourth metal interconnection 135 serving as the output terminal of the first cell 121 and to the third metal interconnection 134 serving as the input terminal of the third cell 123; 138 designates a third signal line connected to the fourth metal interconnection 135 serving as the output terminal of the third cell 123; 139 designates a fourth signal line connected to the third metal interconnection 134 serving as the input terminal of the second cell 122; 140 designates a fifth signal line connected to the fourth metal interconnection 135 serving as the output terminal of the second cell 122, and to the third metal interconnection 134 serving as the input terminal of the fourth cell 124; and 141 designates a sixth signal line connected to the fourth metal interconnection 135 serving as the output terminal of the fourth cell 124.
The first metal interconnections 132 of the first and second cells 121 and 122 are connected to the first power supply main 125, and the first metal interconnections 132 of the third and fourth cells 123 and 124 are connected to the second power supply main 126. In addition, the second metal interconnections 133 of the first to fourth cells 121–124 are connected to the ground main 127.
In the conventional system, the power supply potentials of the individual cells are determined in advance. For example, the individual cells are connected to the nearest power supply mains as shown in FIG. 19. Thus, the power supply potentials of the individual cells are equal to the potentials of the nearest power supply mains.
With the foregoing configuration, the conventional automatic placement and routing apparatus and automatic placement and routing method control the timing of the semiconductor integrated circuit by altering the cell placement, routing and logic. Accordingly, meeting the timing constraint is likely to be time consuming.